`timescale 10ns / 1ps

module uart_top_tb ();

    reg clk_50m;
    reg rst_n;
    reg rx;
    wire tx;

    initial begin
        $dumpfile("output/uart_top_tb.vcd");
        $dumpvars(0, uart_top_tb);
    end
  
    initial begin
        clk_50m = 0;
        rst_n =0;
        #10 rst_n =1;
        #5_000_000 $stop;
    end

    always #1 clk_50m = ~clk_50m;
   
    uart_top inst_top(
    	.clk_50m		(clk_50m),
    	.rst_n			(rst_n),
    	.rx				(rx),
    	.tx				(tx)
    );

endmodule  //uart_top_tb